CRYSTAL
 3rd OVERTONE
DUAL-MODE
OSCILLATOR
FUNDAMENTAL
MODE
Divide by
3
COUNTER
Clock
N1 out
NON-VOLATILE
MEMORY
MICRO-
COMPUTER
DIRECT
DIGITAL
SYNTHESIZER
Divide
by
4000
Divide
by
2500
PHASE-
LOCKED
LOOP
VCXO
10 MHz
output
F
F
T
1 PPS
output
T = Timing Mode
F = Frequency Mode
f3 = 10 MHz - fd
f1
Mixer
fb
N2
Clock
Clock
T
fd
Block Diagram
2-20
MCXO Frequency Summing Method
   In the frequency summing method, the direct digital synthesizer (DDS) generates a correction frequency fd, based on N2, such that f3 + fd = 10 MHz at all temperatures.  The phase locked loop locks the VCXO to this precise 10 MHz.
   In the “frequency mode,” the 1 PPS output is derived by division from 10 MHz.  In the power conserving “timing mode,” the 1 PPS is generated directly from f3 driving the DDS, and by using a different calibration equation.  The PLL and portions of the digital circuitry are turned off, the microprocessor goes to “sleep” between corrections, and the time between corrections is increased to reduce the power requirement.


A. Benjaminson and S. Stallings, "A Microcomputer-Compensated Crystal Oscillator Using Dual-Mode Resonator," Proc. 43rd Annual Symposium on Frequency Control, pp. 20-26, 1989, IEEE Catalog No. 89CH2690-6.

A. Benjaminson and B. Rose, "Performance Tests on an MCXO Combining ASIC and Hybrid Construction," Proc. 45th Annual Symposium on Frequency Control, pp. 393-397, IEEE pub. no. 91CH2965-2, 1991.

E. Jackson, H. Phillips, B. E. Rose, "The Micro-computer Compensated Crystal Oscillator - A Progress Report," Proc. 1996 IEEE Int'l Frequency Control Symposium, pp. 687-692, IEEE pub. no. 96CH35935, 1996.